Intel will launch its latest processor generation this spring, despite a minor setback in ultra-low voltage models designed for super-slim notebooks. By normal standards, the launch should mark a new "tick" in the company's product roadmap, but Intel goes beyond simply shrinking the current 32nm Sandy Bridge processor by making some fundamental advances along with its new 22 -nm process introduces.
For unknowns, Intel is following a "tick-tock" model for its processor upgrade cycle. With each "tick", the company changes to a smaller manufacturing process, in this case from 32 nm to 22 nm, which dramatically increases transistor density while improving the performance and energy efficiency of the current microarchitecture. Then Intel introduces a new processor microarchitecture with an alternating "tock" cycle.
Ivy Bridge includes manufacturing and subsystem improvements. It is a shrink from Sandy Bridge and for us it is also the first tri-gate transistor from Intel that uses a non-planar architecture to pack more transistors in less space, therefore using less power or delivering more power within the same power envelope.
Since Intel described the architecture in detail at the end of last year, there has been a lot of information about Ivy Bridge. We'll summarize some of the key changes and practical implications while keeping you updated on the latest developments, including the expected grid and specs.
Tri-gate transistors = improved efficiency and performance
Unlike conventional planar transistors that lie flat, Ivy Bridge's tri-gate transistors use a three-dimensional fin that is vertical to the silicon substrate. This has several advantages. For starters, Intel can pack more transistors in less space, which is incredibly valuable when manufacturing technology shrinks to 22 nm and more.
In addition, the new design essentially enables the triple surface on which electrons can move when the transistor is on, paving the way for higher performance.
Transistors transmit an electrical signal, while gates control this flow by turning the current on and off. While in a typical transistor only the small layer between the channel and the gate becomes active when the transistor is turned on, Intel's tri-gate transistor creates a three-sided silicon fin that wraps around the gate, thereby increasing the surface area on the actually electrical current flows flowing. The following video explains this better.
This design also maximizes transistor switching power between on and off states and reduces power dissipation.
Intel summarizes the practical implications by saying that the 22nm 3D tri-gate transistors at low operating voltages increase performance by up to 37% over Intel's 32nm planar transistors – a big deal for atomic and ULV chips – or at 1 V almost 20% bid for high-end desktop and mobile parts.
Alternatively, the new 22nm tri-gate transistors can consume less than half the power if they have the same performance level as 2D planar transistors on 32nm chips.
Intel has also mentioned the possibility that multiple ridges stand vertically from the silicon substrate and are interconnected as shown on the right to increase the overall drive power of the transistor for higher performance. They haven't discussed this in detail, but we're assuming that Intel could use it to fine-tune its 22nm process in high-end products, or use it as a fail-safe method to increase individual chip yields improve.
The new 22nm tri-gate wafers shouldn't be much more expensive to manufacture either. Compared to a hypothetical planar Intel 22 nm process, the 3D tri-gate process should, according to Intel's own estimates, only contribute a further 2-3% to the total costs.
Other architectural changes
In addition to the new transistor design, there are no significant changes in the Ivy Bridge architecture compared to Sandy Bridge. It continues the 2-chip platform partition (CPU + PCH) and is backwards compatible with existing LGA-1155 motherboards, although there will be new chipsets to enable new features.
The central part of the chip has four x86-64 cores, each with 256 KB dedicated L2 cache and a shared 8 MB L3 cache. The system agent and graphics core are located on each side of this central section.
All of these components are linked to a ring bus that transports data between them. The system agent has interfaces for the integrated two-channel DDR3 memory controller, the PCI Express controller (supports 16 PCIe 3.0 lanes), the DMI chipset bus, a display controller and an FDI connection to the PCH.
But there are a few improvements here and there. First and foremost, the graphics core has been completely redesigned and now supports OpenCL 1.1, DirectX 11 and OpenGL 3.1. This will finally bring the integrated Intel GPU to parity with AMDs. Intel also added a graphics-specific L3 cache, three display outputs (two in Sandy Bridge), better anisotropic filtering, more shaders or execution units (depending on the GPU 8 or 16 EUs in Ivy Bridge versus 6 or 12 in Sandy) Bridge ) and some other improvements.
Ivy Bridge also significantly improves Intel Quick Sync Video, the chip giant's transcoding technology. Overall, the bottom line is an increase in GPU performance of up to 60% over Sandy Bridge's built-in GPU.
Hyper-Threading and CPU instruction set changes On the CPU side there are some changes in the way resource allocation is done for the HyperThreading queue. Ivy Bridge dynamically allocates resources to threads so that when only a single thread is active, all resources are allocated to that thread and not some remain unused as with static assignment of SB.
There is a new random number generation process that improves security, an energy management feature that offers more flexibility in adjusting a system's thermal envelope (more on this below), and improvements in memory and string performance. Ivy Bridge has also reportedly enabled more dynamic overclocking.
On the next two pages: Ivy Bridge's performance optimizations as well as the starting lines confirmed by the CPU and chipset.